integrated circuit systems, inc. general description features ics9148-47 block diagram pentium/pro tm system clock chip 9148-47 rev d 08/04/98 pin configuration 28 pin soic pentium is a trademark on intel corporation. ? generates system clocks for cpu, pci, ioapic , 14.314 mhz, 48 and 24mhz. ? supports single or dual processor systems ? skew from cpu (earlier) to pci clock 1 to 4ns ? separate 2.5v and 3.3v supply pins ? 2.5v outputs: cpu, ioapic ? 3.3v outputs: pci, ref ? no power supply sequence requirements ? 28 pin soic ? spread sectrum operation optional for pll1 ? cpu frequencies to 100mhz are supported. the ics9148-47 is part of a reduced pin count two-chip clock solution for designs using an intel bx style chipset. companion sdram buffers are ics9179-11 and ?12. there are two plls, with the first pll capable of spread spectrum operation. spread spectrum typically reduces system emi by 8-10db. the second pll provides support for usb (48mhz) and 24mhz requirements. cpu frequencies up to 100mhz are supported. the i 2 c interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. clock outputs include two cpu (2.5v or 3.3v), seven pci (3.3v), one ref (3.3v), one ioapic (2.5v or 3.3v), one 48mhz, and one selectable 48/24mhz. ground groups gnd = ground source core gnd1 = ref0, x1, x2 gnd2 = pciclk_f, pciclk (0:5) gnd3=48mhz gndl = cpuclk (0:1) power groups vdd = supply for pll core vdd1 = ref0, x1, x2 vdd2 = pciclk_f, pciclk (0:5) vdd3 = 48mhz vddl = cpuclk (0:1) vddl1=ioapic ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9148-47 pin descriptions pin number pin name type description 1x1in xtal_in 14.318mhz crystal input, has internal 33pf load cap and feed back resistor from x2 2 x2 out xtal_out crystal output, has internal load cap 33pf 3 gnd2 pwr ground for pci outputs 4 pciclk_f out free running pci output 5, 6, 7, 8, 10, 11 pciclk (0:5) out pci clock outputs. ttl compatible 3.3v 6, 9 vdd2 pwr power for pciclk outputs, nominally 3.3v 12 vdd3 pwr poer for 48mhz 13 48mhz out fixed clk output @ 48mhz 14 24/48mhz out fixed clk output; 24mhz if pin 27 =1 at power up, 48mhz if pin 27=0 at power up. 15 gnd3 pwr ground for 48mhz 16 sel100/66.6# in select pin for enabling 100mhz or 66.6mhz h=100mhz, l=66.6mhz (pci always synchronous 33.3mhz) 17 sclk in clock input for i 2 c input 18 sdata in data input for i 2 c input 19 gnd pwr ground for cpuclk (0:1) 20 vdd pwr power for pll core 21, 22 cpuclk (1:0) out cpu and host clock outputs nominally 2.5v 23 vddl pwr power for cpu outputs, nominally 2.5v 24 ioapic out ioapic clock output 14.318mhz. 25 vddl pwr power for ioapic 26 vdd1 pwr power for ref outputs. 27 ref0/sel 48# out/in 14.318mhz clock output/latched input at power up. when low, pin 14 is 48mhz. 28 gnd1 pwr ground for ref outputs, x1, x2.
3 ics9148-47 general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? send the address d2 (h) . ? send two additional dummy bytes, a command code and byte count. ? send the desired number of data bytes. see the diagram below: note that the acknowledge bit is sent by the clock chip, and pulls the data line low. there is no minimum of data bytes that mu st be sent. how to read: ? send the address d3 (h) . ? send the byte count in binary coded decimal ? read back the desired number of data bytes see the diagram below: the following specifications should be observed: 1. operating voltage for i 2 c pins is 3.3v 2. maximum data transfer rate (sclk) is 100k bits/sec. clock generator address (7 bits) ack + 8 bits dummy command code ack + 8 bits dummy byte count ack data byte 1 ack data byte n ack a(6:0) & r/w# d2 (h) clock generator address (7 bits) ack byte count ack data byte 1 ack data byte n a(6:0) & r/w# d3(h)
4 ics9148-47 note: pwd = power-up default byte 3: functionality & frequency select & spread slect register notes: 1 = enabled; 0 = disabled, outputs held low bit description pwd 7(reserved)0 6:4 bit 654 cpu pci spread percentage 000 001 010 011 100 101 110 111 68.5 75.0 83.3 66.6 103 112 133.3 100 34.25 37.5 41.6 33.3 34.3 37.3 44.43 33.33 0.5% center 0.5% center 0.5% center 0.5% center 0.5% center 0.5% center 0.5% center 0.5% center 0 3 0 - frequency is selected by hardware select sel100/66.6# 1 - frequency is selected by 6:4 above 0 2(reserved) 10 00 - normal operation 01 - test mode 10 - spread sprectrum on 11 - tristate all outputs 00 byte 4: notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pin name pwd description bit value = 0 bit value = 1 7 - - - (reserved) (reserved) 6 - - - (reserved) (reserved) 5 - - - (reserved) (reserved) 4 - - - (reserved) (reserved) 3 - - - (reserved) (reserved) 221cpuclk11 disabled (low) enabled 1 - - 0 (reserved) (reserved) 022cpuclk01 (disabled) (low) enabled byte 5: notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pin name pwd description bit value = 0 bit value = 1 74pciclk_f1 disabled (low) enabled 6 11 pciclk5 1 disabled (low) enabled 5 10 pciclk4 1 disabled (low) enabled 4 - - 0 (reserved) (reserved) 38pciclk31 disabled (low) enabled 27pciclk21 disabled (low) enabled 16pciclk11 disabled (low) enabled 05pciclk01 disabled (low) enabled serial bitmap byte 6: notes: 1 = enabled; 0 = disabled, outputs held low for pin 27, there are 2 output stages together for 1 pin. these 2 latches must be both 0 or 1 simultaneously or there will be a short to ground if one is disabled and the other is running. bit pin# pin name pwd description bit value = 0 bit value = 1 7 - - 0 (reserved) (reserved) 6 - - 0 (reserved) (reserved) 524ioapic 1 disabled (low) enabled 4 - - 0 (reserved) (reserved) 3 - - 0 (reserved) (reserved) 2 - - 0 (reserved) (reserved) 127 ref0 1 (disabled) (low) enabled 027 ref0 1 (disabled) (low) enabled
5 ics9148-47 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3.3op66 c l = 0 pf; select @ 66mhz 60 170 ma supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 66 170 power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 3 650 m a supply current input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t agp-pci1 v t = 1.5 v; 13.54 ns 1 guaranteed by design, not 100% tested in production.
6 ics9148-47 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 16 72 ma supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 23 100 ma power down supply current i dd2 .5 pd c l = 0 pf; with input address to vdd or gnd 10 100 m a t cpu-agp 00.51 ns t cp u-p ci2 v t = 1.5 v; v tl = 1.25 v 12.64 ns 1 guaranteed by des ign, not 100% tes ted in production. skew 1 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.2 0.4 v output high current i oh2 b v oh = 1.7 v -41 -19 ma output low current i ol2 b v ol = 0.7 v 19 37 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.25 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% skew t sk2b 1 v t = 1.25 v 30 175 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 150 250 ps jitter, one sigma t j1s2b 1 v t = 1.25 v 40 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 140 +250 ps 1 guaranteed by design, not 100% tested in production.
7 ics9148-47 electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.1 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 140 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 70 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh4b i oh = -18 ma 2 2.2 v output low voltage v ol4b i ol = 18 ma 0.33 0.4 v output high current i oh4b v oh = 1.7 v -41 -28 ma output low current i ol4b v ol = 0.7 v 29 37 ma ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.3 1.6 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 54 55 % skew 1 t sk4b 1 v t = 1.25 v 60 250 ps jitter, one sigma 1 t j1s4b v t = 1.25 v 1 3 % jitter, absolute 1 t jabs4b v t = 1.25 v -5 5 % 1 guaranteed by design, not 100% tested in production.
8 ics9148-47 electrical characteristics - 48, 24 mhz t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3 v output low voltage v ol5 i ol = 9 ma 0.14 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 16 42 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.2 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52 55 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3.1 v output low voltage v ol5 i ol = 9 ma 0.17 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 29 42 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t5 v t = 1.5 v 47 54 57 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
9 ics9148-47 soic package lead count 28l dimension l 0.704 ordering information ics9148m-47 pattern number (2 or 3 digit number for parts with rom code patterns) package type m=soic device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx m - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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